SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 970

• Manufacturer Part Number: SAM9G45
• Manufacturer: Atmel Corporation

Specifications of SAM9G45

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 41-10. DMAC Transfer Flow for Source and Destination Address Auto-reloaded
41.4.5.5
970
SAM9G45
Multi-buffer Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row 6)
HDMA Transfer Complete
Interrupt generated here
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of linked list items (otherwise known as buffer descriptors) in memory.
Write the control information in the LLI.DMAC_CTRLAx and DMAC_CTRLBx registers
location of the buffer descriptor for each LLI in memory for channel x. For example, in
the register you can program the following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_WIDTH field.
– ii. Transfer width for the destination in the DST_WIDTH field.
– iii. Source AHB master interface layer in the SIF field where source resides.
– iv. Destination AHB master interface layer in the DIF field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
– vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
Channel Disabled by
nation) and flow control peripheral by programming the FC of the DMAC_CTRLBx
register.
hardware
Buffer Complete interrupt
generated here
yes
Stall until STALLED is cleared
DADDRx, CTRLAx, CTRLBx
Replay mode for SADDRx,
by writing to KEEPON field
HDMA State Machine table?
Channel Enabled by
Is HDMA in Row1 of
EBCIMR[x]=1?
Buffer Transfer
software
yes
no
no
6438G–ATARM–19-Apr-11