SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 183
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SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 183 of 1196
- Download datasheet (20Mb)
21. Static Memory Controller (SMC)
21.1
21.2
Table 21-1.
21.3
Table 21-2.
6438G–ATARM–19-Apr-11
Name
NCS[7:0]
NRD
NWR0/NWE
A0/NBS0
NWR1/NBS1
A1/NWR2/NBS2
NWR3/NBS3
A[25:2]
D[31:0]
NWAIT
NWR0
A0
NWR1
A1
NWR3
Description
I/O Lines Description
Multiplexed Signals
Multiplexed Signals
NWE
NBS0
NBS1
NWR2
NBS3
I/O Line Description
Static Memory Controller (SMC) Multiplexed Signals
Description
Static Memory Controller Chip Select Lines
Read Signal
Write 0/Write Enable Signal
Address Bit 0/Byte 0 Select Signal
Write 1/Byte 1 Select Signal
Address Bit 1/Write 2/Byte 2 Select Signal
Write 3/Byte 3 Select Signal
Address Bus
Data Bus
External Wait Signal
The Static Memory Controller (SMC) generates the signals that control the access to the exter-
nal memory devices or peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The
32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate
read and write control signals allow for direct memory and peripheral interfacing. Read and write
signal waveforms are fully parametrizable.
The SMC can manage wait requests from external devices to extend the current access. The
SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-
programmed waveforms to slow-rate specific waveforms on read and write signals. The SMC
supports asynchronous burst read in page mode access for page size up to 32 bytes.
NBS2
Related Function
Byte-write or byte-select access, see
8-bit or 16-/32-bit data bus, see
Byte-write or byte-select access see
8-/16-bit or 32-bit data bus, see
Byte-write or byte-select access, see
Byte-write or byte-select access see
“Data Bus Width” on page 185
“Data Bus Width” on page
“Byte Write or Byte Select Access” on page 185
“Byte Write or Byte Select Access” on page 185
“Byte Write or Byte Select Access” on page 185
“Byte Write or Byte Select Access” on page 185
185.
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
I/O
SAM9G45
Active Level
Low
Low
Low
Low
Low
Low
Low
Low
183
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