AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 83

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

13.3
3714A–MICRO–7/11
Mode 1 – 16-bit Auto-Reload Timer/Counter
Figure 13-1. Timer/Counter 1 Mode 0: Variable Width Counter
In Mode 1 the Timers are configured for 16-bit auto-reload. The Timer register is run with all
16 bits. The 16-bit reload value is stored in the high and low reload registers (RH1/RL1). The
clock is applied to the combined high and low timer registers (TH1/TL1). As clock pulses are
received, the timer counts up: 0000H, 0001H, 0002H, etc. An overflow occurs on the FFFFH-to-
0000H transition, upon which the timer register is reloaded with the value from RH1/RL1 and the
overflow flag bit in TCON is set. See
gives the full 16-bit timer period compatible with the standard 8051. Mode 1 operation is the
same for Timer/Counter 0.
The following equation gives the timeout period for Mode 1. In Fast Mode, TPS applies only
when the TnX2 bits in CKCON0 are set. TPS always applies in Compatibility Mode, therefore
setting TnX2 in Compatibility Mode will double the timeout period.
Figure 13-2. Timer/Counter 1 Mode 1: 16-bit Auto-Reload
INT1 Pin
GATE1
INT1 Pin
T1 Pin
CLK
GATE1
CLK
T1 Pin
SYS
SYS
Mode 1:
TR1
÷TPS
TR1
÷TPS
C/T = 0
C/T = 1
Time-out Period
C/T = 0
C/T =1
AT89LP51RD2/ED2/ID2 Preliminary
Control
Control
Figure
13-2. The reload registers default to 0000H, which
=
(
---------------------------------------------------------
65536
(8 Bits)
TL1
(8 Bits)
(8 Bits)
RL1
TL1
–
f
{
SYS
RHn RLn
(8 Bits)
(8 Bits)
(8 Bits)
RH1
TH1
TH1
,
PSC1
}
)
×
Reload
(
TPS
TF1
TF1
+
1
)
Inter r up t
Inter r up t
83