AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 170

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

21.4
170
Clock Selection
AT89LP51RD2/ED2/ID2 Preliminary
output channels and the DIFF, ACON and ACS bits have no effect in DAC mode. P2.2 and P2.3
are automatically forced to input-only mode while the DAC is enabled.
A timing diagram of a DAC conversion is shown in
clock cycles to complete. Construction of the analog output starts in the second cycle of the con-
version and the DAC will allow the new value to propagate to the outputs during cycle 7, after the
5 MSBs are complete. At the end of the conversion, the interrupt flag is set. An additional 1 ADC
clock cycle and up to 2 system clock cycles may be required to synchronize ADIF with the rest of
the system. The DADL and DADH registers hold the value to be output and are write-only during
DAC mode. An internal buffer samples DADH/DADL at the start of the conversion and holds the
value constant for the remainder of the conversion. One system clock cycle is required to trans-
fer the contents of DADH/DADL into the buffer at the start of the conversion and therefore the
ADC clock frequency must always be equal to or less than the system clock frequency during
DAC mode to ensure that the buffer is updated before the second cycle.
Figure 21-4. DAC Timing Diagram
The equivalent model for the analog output circuitry is illustrated in
put resistance of the DAC must drive the pin capacitance and any external load on the pin.
Figure 21-5. Equivalent Analog Output Model
The DADC requires a clock of 2 MHz or less to achieve full resolution. By default the DADC will
use an internal 2 MHz clock generated from the 8 MHz internal oscillator. The internal oscillator
will be enabled even if it is not supplying the system clock. This may result in higher power con-
sumption. Conversely, the DADC clock can be generated directly from the system oscillator
using a 7-bit prescaler. The prescaler output is controlled by the ACK bits in DADC as shown in
Figure
Cycle Number
ADC Clock
GO/BSY
ADIF
DADH
DADL
21-6. The prescaler is independent of any X2 or CKRL division used for the CPU clock.
1
2
V
Initialize Circuitry
OUT
3
AV
MSB of Output
LSB of Output
DD
Begin Output
4
/2
R
100 kΩ
OUT
One Conversion
5
=
6
7
8
Figure
Conversion
Complete
9
C
21-4. The conversion requires 11 ADC
10 pF
10
PIN
=
11
Figure
DAn
Next Conversion
1
21-5. The series out-
2
Initialize
3714A–MICRO–7/11
3