AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 39

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 5-5.
Table 5-6.
Table 5-7.
3714A–MICRO–7/11
Symbol
ENBOOT
XSTK
GF3
DPS
Symbol
DPU1
DPU0
DPD1
DPD0
DPD1
0
0
1
1
AUXR1 = A2H
Not Bit Addressable
Bit
DPCF = A1H
Not Bit Addressable
Bit
DPD0
Function
Set ENBOOT = 1 to map the Boot ROM in the range F800H–FFFFH. This is required to run the bootloader or access the
Flash API. When ENBOOT = 0 the Boot ROM is not accessible and normal program memory is mapped to this range.
The default value is set by the Bootloader Jump bit. See
Extended Stack Enable. When XSTK = 0 the stack resides in IDATA and is limited to 256 bytes. Set XSTK = 1 to place
the stack in EDATA for up to 2K bytes of extended stack space. All PUSH, POP, CALL and RET instructions will incur a
one or two cycle penalty when accessing the extended stack.
This bit is a general purpose user flag.
Data Pointer Select. DPS selects the active data pointer for instructions that reference DPTR. When DPS = 0, DPTR will
target DPTR0 and /DPTR will target DPTR1. When DPS = 1, DPTR will target DPTR1 and /DPTR will target DPTR0.
Function
Data Pointer 1 Update. When set, MOVX @DPTR and MOVC @DPTR instructions that use DPTR1 will also update
DPTR1 based on DPD1. If DPD1 = 0 the operation is post-increment and if DPD1 = 1 the operation is post-decrement.
When DPU1 = 0, DPTR1 is not updated.
Data Pointer 0 Update. When set, MOVX @DPTR and MOVC @DPTR instructions that use DPTR0 will also update
DPTR0 based on DPD0. If DPD0 = 0 the operation is post-increment and if DPD0 = 1 the operation is post-decrement.
When DPU0 = 0, DPTR0 is not updated.
Data Pointer 1 Decrement. When set, INC DPTR instructions targeted to DPTR1 will decrement DPTR1. When cleared,
INC DPTR instructions will increment DPTR1. DPD1 also determines the direction of auto-update for DPTR1 when
DPU1 = 1.
Data Pointer 0 Decrement. When set, INC DPTR instructions targeted to DPTR0 will decrement DPTR0. When cleared,
INC DPTR instructions will increment DPTR0. DPD0 also determines the direction of auto-update for DPTR0 when
DPU0 = 1.
Data Pointer Auto-Update
0
1
0
1
AUXR1
DPCF
DPU1
–
7
7
– Data Pointer Configuration Register
– Auxiliary Register 1
DPTR0++
DPTR0++
DPTR0--
DPTR0--
DPTR
DPU0
Update Operation for MOVX and MOVC (DPU1 = 1 & DPU0 = 1)
–
6
6
DPS = 0
ENBOOT
DPD1
DPTR1++
DPTR1++
5
5
DPTR1--
DPTR1--
/DPTR
AT89LP51RD2/ED2/ID2 Preliminary
DPD0
XSTK
4
4
DPTR1++
DPTR1++
DPTR1--
DPTR1--
DPTR
Section 24.2 on page
GF3
3
–
3
DPS = 1
DPTR0++
DPTR0++
DPTR0--
DPTR0--
/DPTR
0
2
–
2
190.
Reset Value = XXX0 00X0B
Reset Value = 0000 XXXXB
–
1
–
1
DPS
0
–
0
39