AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 185

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

23. On-Chip Debug System
23.1
3714A–MICRO–7/11
Physical Interface
The AT89LP51RD2/ED2/ID2 On-Chip Debug (OCD) System uses a two-wire serial interface to
control program flow; read, modify, and write the system state; and program the nonvolatile
memory. The OCD System has the following features:
The On-Chip Debug System uses a two-wire synchronous serial interface to establish communi-
cation between the target device and the controlling emulator system. The OCD interface is
enabled by clearing the OCD Enable Fuse. The OCD device connections are shown in
23-1. When OCD is enabled, the RST port pin is configured as an input for the Debug Clock
(DCL). P4.3 is a bi-directional data line for the Debug Data (DDA).
When designing a system where On-Chip Debug will be used, the following observations must
be considered for correct operation:
Figure 23-1. AT89LP51RD2/ED2/ID2 On-Chip Debug Connections
• Complete program flow control
• Read-Modify-Write access to all internal SFRs and data memories
• Four hardware program address breakpoints
• Four program/data address breakpoints configurable in 2 maskable pairs.
• Unlimited program software breakpoints using BREAK instruction
• Break on change in program memory flow
• Break on stack overflow/underflow
• Break on Watchdog overflow
• Break on reset
• Non-intrusive operation
• Programming of nonvolatile memory
• RST cannot be connected directly to V
• All external reset sources must be removed.
• OCD is shipped disabled from the factory. A device programmer is required to enable this
• Enabling OCD disables the RST input and thereby disables the In-System Programming
connected to RST must be removed.
fuse before debugging can occur.
interface (ISP). ISP can only be re-entered by holding RST active at power-up. The
bootloader remains active and has priority over the OCD system.
GND or VDD
AT89LP51RD2/ED2/ID2 Preliminary
DCL
AT89LP51RD2/ED2/ID2
DD
RST
POL
GND
or GND and any external capacitors or supervisors
VDD
P4.3
DDA
Figure
185