AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 47

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

6.6.1
6.6.2
6.6.3
3714A–MICRO–7/11
Normal Operation
Idle Operation
Power-down Operation
BEn bits in OSCCON. The oscillator selection at reset is controlled by the Oscillator Select user
fuse (See
loader Hardware Security Byte. The fuse sets the CKS, OscAEn and OscBEn bits as shown in
Table
Table 6-3.
Only a single oscillator source can drive the system clock at any one time. Under normal condi-
tions it is always possible to dynamically switch from OSCA to OSCB or vice-versa by changing
the CKS bit. The procedure is as follows:
The clock system hardware will prevent the disabling of the current active oscillator and will pre-
vent switching to a disabled oscillator. However, the hardware will not prevent switching to an
oscillator before it has stabilized. The application software must ensure enough delay between
enabling an oscillator and switching to that oscillator so that the oscillator source can stabilize.
This is generally only an issue when using one of the crystal oscillators.
Any enabled oscillator will continue to function during Idle mode. Power can be reduced by dis-
abling the alternate oscillator before entering Idle mode. Once in Idle mode, the oscillator source
cannot be changed until the mode is exited. An interrupt exit from Idle will leave the oscillator
control bits (OscAEn, OscBEn and CKS) unchanged. Any reset will exit Idle mode and place
these bits in their default states as determined by the user fuse.
All oscillators are stopped during Power-down mode. Once in Power-down mode, the oscillator
source cannot be changed until the mode is exited. An interrupt exit from Power-down will leave
the oscillator control bits (OscAEn, OscBEn and CKS) unchanged. Any reset will exit Power-
down mode and place these bits in their default states as determined by the user fuse.
Control Bit
OscAEn (OSCCON.0)
OscBEn (OSSCON.1)
CKS (CKSEL.0)
1. Enable the desired oscillator by setting the OscAEn or OscBEn bits in OSCCON
2. Wait for the oscillator to stabilize. This can be a very long time when using the 32 kHz
3. Change CKS to switch the system clock source. This takes at most 2 periods of each
4. Disable the previous oscillator by clearing the OscAEn or OscBEn bits in OSCCON
5. Note that unlike AT89C51ID2, the OSCB source is affected by both X2 and the CKRL
oscillator. The application software must ensure that the delay is long enough for the
operating conditions
oscillator
divider. When changing the clock source, the X2 and CKRL values may need to be
updated to achieve the desired frequency
6-3.
Section 24.2 on page
Oscillator Reset States
AT89LP51RD2/ED2/ID2 Preliminary
190). This fuse is also shadowed in the OSC bit of the boot-
00H (0)
Oscillator Select Fuse
0
1
0
(HSB.OSC)
FFH (1)
0
1
1
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