AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 205

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

24.5.2.2
24.5.2.3
3714A–MICRO–7/11
Flash Memory Lock Bits
Software Registers
The three lock bits provide different levels of protection for the on-chip code and data when pro-
grammed as shown in
Bits (See
Table 24-13. Program Lock Bits
Note:
Several registers are used in by the bootloader for the boot process. These registers are in the
User Signature part of the Flash memory. They are accessed in the following ways:
Several software registers are described in
Table 24-14. Bootloader Software Registers
After programming the part by the bootloader, the BSB must be cleared (00h) in order to allow
the application to boot at 0000h.
The content of the Software Security Byte (SSB) is described in
The SSB protects the Flash memory from programming by the bootloader the same way the
Hardware Security bits protect from ISP.
• Commands issued by the ISP programmer
• Commands issued by the Bootloader software.
• API calls issued by the application software.
Security
Mnemonic
Level
SBV
BSB
SSB
1
2
3
4
Program Lock Bits
U: Unprogrammed or "one" level.
P: Programmed or "zero" level.
X: Do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code verification.
Section 24.3 on page
LB0
U
P
X
X
Definition
Software Boot Vector
Boot Status Byte
Software Security Byte
LB1
U
U
P
X
Table
LB2
U
U
U
P
AT89LP51RD2/ED2/ID2 Preliminary
24-13. These bits in the HSB are copies of the Hardware Security
191).
Protection Description
No program lock features enabled.
MOVC instruction executed from external program memory is disabled from
fetching code bytes from internal memory, EA is sampled and latched on reset,
and further parallel programming of the on chip code memory is disabled.
ISP and software programming with API are still allowed.
Same as 2, also verify code memory through parallel programming interface is
disabled.
Same as 3, also external execution is disabled (Default).
Table
24-14.
Default value
FCh
FFh
FFh
Table 24-15
and
Table
24-16.
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