AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 156

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

19.6.4
Figure 19-14. Format and States in Slave Transmitter Mode
156
Reception of the own
slave address and one or
more data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
AT89LP51RD2/ED2/ID2 Preliminary
Slave Transmitter Mode
From master to slave
From slave to master
S
In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver. To
initiate the Slave Transmitter mode, upper 7 bits of SSADR must be initialized with the address
to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is
set, the TWI will respond to the general call address (00h), otherwise it will ignore the general
call address. SSIE must be written to one to enable the TWI. The AA bit must be written to one
to enable the acknowledgment of the device’s own slave address or the general call address.
STA and STO must be written to zero.
When SSADR and SSCON have been initialized, the TWI waits until it is addressed by its own
slave address (or the general call address if enabled) followed by the data direction bit. If the
direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After
its own slave address and the write bit have been received, the TWINT flag is set and a valid
status code can be read from SSCS. The status code is used to determine the appropriate soft-
ware action. The appropriate action to be taken for each status code is detailed in
The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the
Master mode (see state B0h).
If the AA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer.
State C0h or state C8h will be entered, depending on whether the master receiver transmits a
NACK or ACK after the final byte. The TWI is switched to the not addressed Slave mode, and
will ignore the master if it continues the transfer. Thus the master receiver receives all “1s” as
serial data. State C8h is entered if the master demands additional data bytes (by transmitting
ACK), even though the slave has transmitted the last byte (AA zero and expecting NACK from
the master). While AA is zero, the TWI does not respond to its own slave address. However, the
Two-wire Serial Bus is still monitored and address recognition may resume at any time by set-
ting AA. This implies that the AA bit may be used to temporarily isolate the TWI from the Two-
wire Serial Bus.
SLA
R
DATA
A8h
B0h
A
A
n
A
DATA
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-wire Serial Bus. The
prescaler bits are zero or masked to zero
B8h
A
DATA
C0h
C8h
A
A
P or S
All 1's
3714A–MICRO–7/11
Table
P or S
19-9.