AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 127

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

18. Enhanced Serial Peripheral Interface
3714A–MICRO–7/11
The Serial Peripheral Interface (SPI) allows high-speed, full-duplex synchronous data transfer
between the AT89LP51RD2/ED2/ID2 and peripheral devices or between multiple microcon-
troller devices, including multiple masters and slaves on a single bus. The SPI includes the
following features:
A block diagram of the SPI is shown below in
Figure 18-1. SPI Block Diagram
• Full-duplex, 3-wire or 4-wire Synchronous Data Transfer
• Master or Slave Operation
• Maximum Bit Frequency = f
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates or Timer 1-based Baud Generation (Master Mode)
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Double-buffered Receive and Transmit
• Transmit Buffer Empty Interrupt Flag
• Mode Fault (Master Collision) Detection and Interrupt
• Wake up from Idle Mode
T1 OVF
Clock Select
7-bit Divider
SPI Status Register
F
PERIPH
SPI Control
SPI Clock (Master)
SPI Inter r up t
AT89LP51RD2/ED2/ID2 Preliminary
Request
SYS
/2
MSTR
SPEN
8
MSB
Data Bus
Inte r na l
8
Figure
Read Data Buf f e r
W r ite Data Buf f e r
8-bit Shift Register
8
18-1.
SPI Control Register
Clo c k
Logic
LSB
S
M
M
S
S
M
MISO
MOSI
SCK
SS
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