AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 222

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

24.6.5.4
24.6.5.5
222
AT89LP51RD2/ED2/ID2 Preliminary
ISP Exit Sequence
Serial Peripheral Interface
Figure 24-24. In-System Programming (ISP) Start Sequence
Execute this sequence to exit ISP mode and resume CPU execution mode.
Figure 24-25. In-System Programming (ISP) Exit Sequence
Note:
The Serial Peripheral Interface (SPI) is a byte-oriented full-duplex synchronous serial communi-
cation channel. During In-System Programming, the programmer always acts as the SPI master
and the target device always acts as the SPI slave. The target device receives serial data on
MOSI and outputs serial data on MISO. The Programming Interface implements a standard
SPI Port with a fixed data order and For In-System Programming, bytes are transferred MSB
first as shown in
CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge of
SCK. For more detailed timing information see
1. Drive SCK low.
1. Wait at least t
2. Tristate MOSI.
3. Wait at least t
4. Wait t
The waveforms on this page are not to scale.
XTAL1
XTAL1
MISO
MOSI
MISO
MOSI
RST
SCK
RST
SCK
V
V
SSZ
SS
SS
DD
DD
and tristate SCK.
Figure
SSD
RHZ
.
t
and bring RST low.
SSD
24-26. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0,
t
SSZ
t
RHZ
t
Figure
RLZ
HIGH Z
HIGH Z
24-27.
t
STL
HIGH Z
HIGH Z
t
ZSS
t
SSE
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