AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 194

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

24.4.2
24.4.2.1
194
AT89LP51RD2/ED2/ID2 Preliminary
Low-Level Interface
Mapping of the Memory Space
The CPU interfaces to the Flash memory through the FCON register
register
CAUTION: The incorrect usage of these functions can make the system unstable or inoperable.
For internal execution from user space the AT89LP51RD2/ED2/ID2 uses an idle-while-write
architecture where the CPU is placed in an idle state while programming occurs. When the write
completes, the CPU will continue executing with the instruction after the instruction that started
the write sequence (usually a MOV to FCON). All peripherals will continue to function during the
write cycle; however, interrupts will not be serviced until the write completes.
For external execution from user space the AT89LP51RD2/ED2/ID2 uses an execute-while-
write architecture where the CPU continues to operate while the programming occurs. The soft-
ware should poll the state of the FBUSY flag to determine when the write completes. Interrupts
must be disabled during the write sequence as the CPU will not be able to vector to the internal
interrupt table and care should be taken that the application does not jump to an internal address
until the programming completes.
The Flash API routines in the Boot ROM also use execute-while-write. Interrupts must be dis-
abled before calling the routines to prevent the CPU from vectoring to a non-ROM address
before the programming completes.
Flash memory uses a page-based programming model. Flash data memory differs from tradi-
tional EEPROM data memory in the method of writing data. EEPROM generally can update a
single byte with any value. Flash memory splits programming into write and erase operations. A
Flash write can only program zeroes, i.e change ones into zeroes (
data are ignored. A Flash erase sets an entire page of data to ones so that all bytes become
FFH. Therefore after an erase, each byte in the page can only be written once with any possible
value. Bytes can be overwritten without an erase as long as only ones are changed into zeroes.
However, if even a single bit needs updating from zero to one (
page must first be saved, the entire page must be erased and the zero bits in all bytes (old and
new data combined) must be written. Avoiding unnecessary page erases greatly improves the
endurance of the memory.
By default, the user application space of the Flash Code memory is accessed read-only by the
MOVC instruction. The Flash temporary page buffer is made accessible (write-only) by setting
the FPS bit in FCON register. Writing is possible from 0000H to FFFFF, address bits 6 to 0 are
used to select an address within a page while bits 15 to 7 are used to select the programming
address of the page. Setting FPS takes precedence over the EXTRAM bit in AUXR.
The other memory spaces (User and Atmel Signatures, User Fuses, Hardware Security) are
made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON regis-
ter in accordance with
spaces.
• Map the memory spaces in the addressable space
• Launch the programming of the memory spaces
• Get the status of the Flash memory (busy/not busy)
(Table 3-5 on page
Table
25). These registers are used to:
24-8. A MOVC instruction can then be used for reading these
0
→
1
1
(Table
→
); then the contents of the
0
). Any ones in the write
24-10) and EECON
3714A–MICRO–7/11