AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 142

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

19.3.3
19.3.4
19.3.5
142
AT89LP51RD2/ED2/ID2 Preliminary
Bus Interface Unit
Address Match Unit
Control Unit
Table 19-1.
This unit contains the Data and Address Shift Register (SSDAT), a START/STOP Controller and
Arbitration detection hardware. The SSDAT contains the address or data bytes to be transmit-
ted, or the address or data bytes received. In addition to the 8-bit SSDAT, the Bus Interface Unit
also contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK
Register is not directly accessible by the application software. However, when receiving, it can
be set or cleared by manipulating the TWI Control Register (SSCON). When in Transmitter
mode, the value of the received (N)ACK bit can be determined by the value in the SSCS. The
START/STOP Controller is responsible for generation and detection of START, REPEATED
START, and STOP conditions.
If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu-
ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost
an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate
status codes generated.
The Address Match unit checks if received address bytes match the 7-bit address in the TWI
Address Register (SSADR). If the TWI General Call Recognition Enable (GC) bit in the SSADR
is written to one, all incoming address bits will also be compared against the General Call
address. Upon an address match, the Control unit is informed, allowing correct action to be
taken. The TWI may or may not acknowledge its address, depending on settings in the SSCON.
The Control unit monitors the TWI bus and generates responses corresponding to settings in the
TWI Control Register (SSCON). When an event requiring the attention of the application occurs
on the TWI bus, the TWI Interrupt Flag (SI) is asserted. In the next clock cycle, the TWI Status
Register (SSCS) is updated with a status code identifying the event. The SSCS only contains
relevant status information when the TWI interrupt flag is asserted. At all other times, the SSCS
contains a special status code indicating that no relevant status information is available. As long
as the SI flag is set, the SCL line is held low. This allows the application software to complete its
tasks before allowing the TWI transmission to continue.
The SI flag is set in the following situations:
CR2
0
0
0
0
1
1
1
1
TWI Bit Rate Configuration
CR1
0
0
1
1
0
0
1
1
CR0
0
1
0
1
0
1
0
1
96 x Timer 1
Division
Overflow
Unused
F
256
224
192
160
120
OSCA
60
0.5 < baud < 62.5
F
OSCA
53.5
62.5
100
200
= 12 MHz
47
75
Bit Rate (kHz)
0.67 < baud < 83
F
OSCA
3714A–MICRO–7/11
133.3
266.6
62.5
71.5
100
= 16 MHz
83