AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 82

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 13-4.
13.2
82
Symbol
PWM1EN
PWM0EN
PSC12
PSC11
PSC10
PSC02
PSC01
PSC00
TCONB = 91H
Not Bit Addressable
Bit
Mode 0 – Variable Width Timer/Counter
AT89LP51RD2/ED2/ID2 Preliminary
Function
Pulse Width Modulation 1 Enable
Set to configure Timer 1 for Pulse Width Modulation output on T1 (P3.5). Clear to disable T1 as an output.
Pulse Width Modulation 0 Enable
Set to configure Timer 0 for Pulse Width Modulation output on T0 (P3.4). Clear to disable T0 as an output.
Timer 1 Prescaler
Prescaler for Timer 1 Mode 0. The number of active bits in TL1 equals PSC1 + 1. After reset PSC1 = 100B which
enables 5 bits of TL1 for compatibility with the 13-bit Mode 0 in AT89C51RD2/ED2/ID2.
Timer 0 Prescaler
Prescaler for Timer 0 Mode 0. The number of active bits in TL0 equals PSC0 + 1. After reset PSC0 = 100B which
enables 5 bits of TL0 for compatibility with the 13-bit Mode 0 in AT89C51RD2/ED2/ID2.
PWM1EN
TCONB
7
– Timer/Counter Control Register B
Both Timers in Mode 0 are 8-bit Counters with a variable prescaler. The prescaler may vary from
1 to 8 bits depending on the PSC bits in TCONB, giving the timer a range of 9 to 16 bits.
By default the timer is configured as a 13-bit timer compatible to Mode 0 in the standard 8051.
Figure 13-1
rolls over from all “1”s to all “0”s, it sets the Timer interrupt flag TF1. The counter input is enabled
to the Timer when TR1 = 1 and either GATE1 = 0 or INT1 = 1. Setting GATE1 = 1 allows the
Timer to be controlled by external input INT1, to facilitate pulse width measurements. TR1 is a
control bit in the TCON register. GATE1 is in TMOD. The 13-bit register consists of all 8 bits of
TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be
ignored. Setting the run flag (TR1) does not clear the registers.
The following equation gives the timeout period for Mode 0. In Fast Mode, TPS applies only
when the TnX2 bits in CKCON0 are set. TPS always applies in Compatibility Mode, therefore
setting TnX2 in Compatibility Mode will double the timeout period.
Mode 0 operation is the same for Timer 0 as for Timer 1, except that TR0, TF0, GATE0 and
INT0 replace the corresponding Timer 1 signals in
one for Timer 1 (TMOD.6) and one for Timer 0 (TMOD.2).
PWM0EN
6
shows the Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count
PSC12
Mode 0:
5
PSC11
Time-out Period
4
PSC10
3
=
256
---------------------------------------- -
Figure
×
PSC02
f
SYS
2
2
PSCn
13-1. There are two different C/T bits,
+
1
Reset Value = 0010 0100B
×
PSC01
(
TPS
1
+
1
)
PSC00
3714A–MICRO–7/11
0