AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 153

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 19-8.
3714A–MICRO–7/11
Status
Code
(SSCS)
60h
68h
70h
78h
80h
Status of the Two-wire
Serial Bus and Two-wire
Serial Interface Hardware
Own SLA+W has been
received; ACK has been
returned
Arbitration lost in SLA+R/W
as master; own SLA+W has
been received; ACK has
been returned
General call address has
been received; ACK has
been returned
Arbitration lost in SLA+R/W
as master; General call
address has been received;
ACK has been returned
Previously addressed with
own SLA+W; data has been
received; ACK has been
returned
Status Codes for Slave Receiver Mode
SSIE must be written to one to enable the TWI. The AA bit must be written to one to enable the
acknowledgment of the device’s own slave address or the general call address. STA and STO
must be written to zero.
When SSADR and SSCON have been initialized, the TWI waits until it is addressed by its own
slave address (or the general call address if enabled) followed by the data direction bit. If the
direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After
its own slave address and the write bit have been received, the SI flag is set and a valid status
code can be read from SSCS. The status code is used to determine the appropriate software
action. The appropriate action to be taken for each status code is detailed in
Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Master
mode (see states 68h and 78h).
If the AA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA after
the next received data byte. This can be used to indicate that the slave is not able to receive any
more bytes. While AA is zero, the TWI does not acknowledge its own slave address. However,
the Two-wire Serial Bus is still monitored and address recognition may resume at any time by
setting AA. This implies that the AA bit may be used to temporarily isolate the TWI from the Two-
wire Serial Bus.
.
To/from SSDAT
No action
No action
No action
No action
No action
No action
No action
No action
Read data byte
Read data byte
Application Software Response
STA
AT89LP51RD2/ED2/ID2 Preliminary
X
X
X
X
X
X
X
X
X
X
STO
0
0
0
0
0
0
0
0
0
0
To SSCON
SI
1
1
1
1
1
1
1
1
1
1
AA
0
1
0
1
0
1
0
1
0
1
Next Action Taken by TWI Hardware
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
Table
19-8. The
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