AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 14

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Figure 3-1.
3.1.1
14
0100
0000
0000
01FF
007F
FFFF
AT89LP51RD2/ED2/ID2 Preliminary
External Program Memory
Atmel Signature Array
Internal Program
User Signature Array
(CODE: 64KB)
ENBOOT = 0
Memory
Program Memory Map
FBS = 0
The AT89LP51RD2/ED2/ID2 implements the entire 16-bit, 64 KB program memory space inter-
nally. The AT89LP51RD2/ED2/ID2 does not support forcing external execution using the EA pin;
however it does include a bank-switching mechanism to allow for up to 32 KB of external pro-
gram memory to be mapped into the upper half of the address space. The FBS bit in the BMSEL
SFR
program memory. FBS can only be modified by instructions executing internally in the range
0000H–7FFFH
The AT89LP51RD2/ED2/ID2 uses the standard 8051 external program memory interface with
the upper address on Port 2, the lower address and data in/out multiplexed on Port 0, and the
ALE and PSEN strobes. Program memory addresses are always 16-bits wide. External program
execution sacrifices two full 8-bit ports, P0 and P2, to the function of addressing the program
memory.
Figure 3-2
a 16-bit linear address. Port 0 serves as a multiplexed address/data bus to the ROM. The
Address Latch Enable strobe (ALE) is used to latch the lower address byte into an external reg-
ister so that Port 0 can be freed for data input/output. Port 2 provides the upper address byte
throughout the operation. PSEN strobes the external memory.
Figure 3-3
stant rate of 1/3 of the system clock with a 1/3 duty cycle. PSEN is emitted at a similar rate, but
with 50% duty cycle. The new address changes in the middle of the ALE pulse for latching on
the falling edge and is tristated at the falling edge of PSEN. The instruction data is sampled from
P0 and latched internally during the high phase of the clock prior to the rising edge of PSEN.
This timing applies to both Compatibility and Fast modes. In Compatibility mode there is no dif-
ference in instruction timing between internal and external execution.
0100
007F
0000
F800
0000
01FF
FFFF
F7FF
(Table
Atmel Signature Array
Internal Program
User Signature Array
shows a hardware configuration for accessing up to 64K bytes of external ROM using
shows the timing of the external program memory interface. ALE is emitted at a con-
(CODE: 62KB)
ENBOOT = 1
3-2) selects whether addresses 8000H–FFFFH are mapped to internal or external
(BOOT: 2KB)
Memory
Boot ROM
FBS = 0
0100
0000
8000
0000
01FF
007F
FFFF
7FFF
Atmel Signature Array
External Program
Internal Program
User Signature Array
(XCODE: 32KB)
(CODE: 32KB)
ENBOOT = 0
Memory
Memory
FBS = 1
0100
007F
0000
F800
8000
0000
01FF
FFFF
F7FF
7FFF
Atmel Signature Array
External Program
Internal Program
User Signature Array
(XCODE: 30KB)
(CODE: 32KB)
ENBOOT = 1
(BOOT: 2KB)
Memory
Memory
Boot ROM
FBS = 1
3714A–MICRO–7/11
SIGEN=1
SIGEN=0