AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 54
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AT89LP51ED2
Manufacturer Part Number
AT89LP51ED2
Description
Manufacturer
Atmel Corporation
Specifications of AT89LP51ED2
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
42
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
7
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
2.25
Eeprom (bytes)
4096
Self Program Memory
API
Operating Voltage (vcc)
2.4 to 5.5
Timers
4
Isp
SPI/OCD/UART
Watchdog
Yes
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7.2
54
Brown-out Reset
AT89LP51RD2/ED2/ID2 Preliminary
Figure 7-2.
Note:
Table 7-1.
The AT89LP51RD2/ED2/ID2 has an on-chip Brown-out Detection (BOD) circuit for monitoring
the V
the BOD is nominally 2.0V. The purpose of the BOD is to ensure that if V
executing at speed, the system will gracefully enter reset without the possibility of errors induced
by incorrect execution. A BOD sequence is shown in
below the trigger level V
above the trigger level plus about 200 mV of hysteresis, the start-up timer releases the internal
reset after the specified time-out period has expired
The BOD does not generate a reset output pulse except as part of a POR event.
SUT Fuse 1
DD
0
0
1
1
t
level during operation by comparing it to a fixed trigger level. The trigger level V
POR
Time-out
Internal
Internal
is approximately 143 µs ± 5%.
Reset
Reset
Power-on Reset Sequence
Start-up Timer Settings
POL
RST
RST
V
DD
SUT Fuse 0
t
POR
V
0
1
0
1
BOD
POR
, the internal reset is immediately activated. When V
V
BOD
Clock Source
Internal RC/External Clock
Crystal Oscillator
Internal RC/External Clock
Crystal Oscillator
Internal RC/External Clock
Crystal Oscillator
Internal RC/External Clock
Crystal Oscillator
output
output
t
SUT
(Table
Figure
(POL Tied to VCC)
input
V
7-1).
7-3. When V
IL
(RST left unconnected)
V
IL
DD
(RST extended
DD
externally)
decreases to a value
t
RHD
fails or dips while
t
SUT
3714A–MICRO–7/11
16384
(± 5%) µs
1024
2048
1024
4096
4096
DD
512
16
increases
BOD
for
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