AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 23

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

3.5.1
3.5.2
3.5.2.1
3714A–MICRO–7/11
Read Protocol
Write Protocol
Byte Write
The following procedure is used to read data stored in the on-chip EEPROM.
The EEPROM address space accesses an internal nonvolatile data memory. Writes to
EEPROM require a more complex protocol and take several milliseconds to complete. The
AT89LP51RD2/ED2/ID2 uses an execute-while-write architecture where the CPU continues to
operate while the EEPROM write occurs. The software must poll the state of the EEBUSY flag to
determine when the write completes. EEPROM data can be written one byte or one page at a
time.
An EEPROM write includes both an erase and write of the affected byte location. A write
sequence will not occur if the Brown-out Detector was active within the last 2 ms. If a write cur-
rently in progress is interrupted by the BOD due to a low voltage condition, the ERR flag
(EECON.2) will be set by hardware.
The following procedure is used to write a single byte to the on-chip EEPROM. See
1. Check EEBUSY flag (EECON.0) and wait for it to go low if necessary
2. Disable interrupts if any interrupt routine accesses external data memory in the range
3. Set bit EEE in EECON register
4. Load DPTR (or DPTRB) with the address to read
5. Execute MOVX A, @DPTR (or MOVX A, @/DPTR)
6. Repeat steps 4–5 for other locations if needed
7. Clear bit EEE in EECON register
8. Restore interrupts if disabled in #2
1. If the write will occur within 2 ms of a reset or power-up event, check the INHIBIT flag
2. Check the EEBUSY flag (EECON.0) and wait for it to go low if necessary
3. Disable interrupts if any interrupt routine accesses external data memory in the range
4. Set bit EEE in EECON register
5. Load DPTR (or DPTRB) with the address to write
6. Load the accumulator (ACC) with the data to be written
7. Execute MOVX @DPTR, A (or MOVX @/DPTR, A)
8. Clear bit EEE in EECON register
9. Restore interrupts if disabled in #3
10. The EEBUSY flag is set by hardware to indicate that programming is in progress and
11. The end of programming is indicated by a hardware clear of EEBUSY
0000H–0FFFH
and wait for it to go high if necessary.
0000H–0FFFH
that the EEPROM is not available for reading and writing
AT89LP51RD2/ED2/ID2 Preliminary
Figure
3-16.
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