AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 230

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 25-4.
Notes:
Figure 25-7. External Program Memory Read Cycle
230
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PLIV
PXIX
PXIZ
PXAV
AVIV
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
QVWH
WHQX
RLAZ
WHAX
WHLH
1. Compatibility Mode timing for MOVX also applies to Fast Mode during exeternal execution of MOVX.
2. This assumes 50% clock duty cycle. The half period depends on the clock high value t
3. This assumes 50% clock duty cycle. The half period depends on the clock low value t
4. In some cases parameter t
5. The strobe pulse width may be lengthened by 1, 2 or 3 additional t
AT89LP51RD2/ED2/ID2 Preliminary
PORT 0
PORT 2
PSEN Low to Valid Instruction In
Input Instruction Hold after PSEN
Input Instruction Float after PSEN
PSEN to Address Valid
Address to Valid Instruction In
PSEN Low to Address Float
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
Data Hold after RD
Data Float after RD
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Valid to WR High
Data Hold after WR
RD Low to Address Float
Address Hold after RD or WR High
RD or WR High to ALE High
PSEN
External Program and Data Memory Characteristics
ALE
(5)
(5)
t
AVLL
LHLL
t
LHLL
may have a minimum of 0.5t
t
LLAX
A0 - A7
t
LLPL
t
AVIV
0.5t
1.5t
2t
1t
4t
1t
1t
0.5t
3t
3t
CLCL
CLCL
CLCL
CLCL
CLCL
A8 - A15
CLCL
CLCL
CLCL
CLCL
CLCL
0
0
t
- d
- d
- d
- d
- d
PLAZ
- d
- d
- d
- d
- d
(2)
(2)
(2)
(3)
(3)
(2)
CLCL
t
t
LLIV
PLIV
INSTR IN
during Fast mode external execution with DISALE = 0.
t
PXIX
1.5t
0.5t
2.5t
4.5t
-1t
1.5t
0.5t
CLCL
2.5t
t
4t
t
PXIZ
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
10
using wait states.
+ d
- d
- d
- d
- d
- d
- d
+ d
+ d
- d
(2)
(2)
(2)
(2)
(2)
t
t
PLPH
PXAV
0.5t
1.5t
0.5t
1.5t
0.5t
0.5t
t
t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCX
CHCX
0
0
A8 - A15
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
A0 - A7
(low duty cycle).
(high duty cycle).
(2)
(2)
(2)
(2)
(3)
(3)
-0.5t
1.5t
0.5t
2.5t
2.5t
2t
t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
10
+ d
- d
- d
- d
- d
- d
- d
- d
+ d
3714A–MICRO–7/11
(2)
(2)
(2)
(2)
(2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns