AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 220

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

24.6.3
Table 24-21.
24.6.4
24.6.5
24.6.5.1
220
Symbol
LOAD
SUCCESS
WRTINH
BUSY
Bit
AT89LP51RD2/ED2/ID2 Preliminary
Status Register
DATA Polling
Programming Interface Timing
Power-up Sequence
Function
Load flag. Cleared low by the load page buffer command and set high by the next memory write. This flag signals that
the page buffer was previously loaded with data by the load page buffer command.
Success flag. Cleared low at the start of a programming cycle and will only be set high if the programming cycle
completes without interruption from the brownout detector.
Write Inhibit flag. Cleared low by the brownout detector (BOD) whenever programming is inhibited due to V
below the minimum required programming voltage. If a BOD episode occurs during programming, the SUCCESS flag
will remain low after the cycle is complete.
Busy flag. Cleared low whenever the memory is busy programming or if write is currently inhibited.
Status
–
7
Register
The current state of the memory may be accessed by reading the status register. The status reg-
ister is shown in
The AT89LP51RD2/ED2/ID2 implements DATA polling to indicate the end of a programming
cycle. While the device is busy, any attempted read of the last byte written will return the data
byte with the MSB complemented. Once the programming cycle has completed, the true value
will be accessible. During Erase the data is assumed to be FFH and DATA polling will return
7FH. When writing multiple bytes in a page, the DATA value will be the last data byte loaded
before programming begins, not the written byte with the highest physical address within the
page.
This section details general system timing sequences and constraints for entering or exiting In-
System Programming as well as parameters related to the Serial Peripheral Interface during
ISP. The general timing parameters for the following waveform figures are listed in section
ing Parameters” on page
Execute this sequence to enter programming mode immediately after power-up. In the RST pin
is disabled or if the ISP Fuse is disabled, this is the only method to enter programming (see
“External Reset” on page
1. Apply power between VDD and GND pins. RST should remain low.
2. Wait at least t
3. Wait at least t
4. Start programming session.
–
6
depend on the current settings of the device.
Table
–
5
PWRUP
SUT
24-21.
for the internal Power-on Reset to complete. The value of t
. and drive RST high if active-high otherwise keep low.
223.
55).
–
4
LOAD
3
SUCCESS
2
WRTINH
1
3714A–MICRO–7/11
BUSY
SUT
0
DD
will
falling
“Tim-