AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 143

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

19.4
Table 19-2.
3714A–MICRO–7/11
SSCON Address = AAH
Not Bit Addressable
Symbol
CR2
SSIE
STA
STO
SI
AA
CR1
CR0
Bit
Register Overview
CR2
Function
Bit Control Rate 2
Sets the bit rate for TWI master mode along with C1 and CR0. See
Two-wire Serial Interface Enable
Set to enable the TWI. Clear to disable the TWI.
Start Flag
Set to send a START condition on the bus. Must be cleared by software.
Stop Flag
Set to send a STOP condition on the bus. Cleared automatically by hardware when the STOP occurs.
Two-wire Interface Interrupt Flag
Set by hardware when the TWI requests an interrupt. SI must be cleared by software. While SI is set, the SCL low period
is stretched. Note that clearing this flag starts the operation of the TWI, so all accesses to the other TWI registers
(SSADR, SSCS and SSDAT) must be complete before clearing this flag.
Assert Acknowledge Flag
Clear in master and slave receiver modes, to force a not acknowledge (high level on SDA). Clear to disable SLA or GCA
recognition. Set to recognize SLA or GCA (if GC set) for entering slave receiver or transmitter modes. Set in master and
slave receiver modes, to force an acknowledge (low level on SDA). This bit has no effect when in master transmitter
mode. By clearing AA to zero, the device can be virtually disconnected from the Two-wire Serial Bus temporarily. Address
recognition can then be resumed by setting the AA bit to one again.
Bit Control Rate 1
Sets the bit rate for TWI master mode along with C0 and CR2. See
Bit Control Rate 02
Sets the bit rate for TWI master mode along with C1 and CR2. See
7
SSCON – Two-Wire Control Register
SSIE
6
• After the TWI has transmitted a START/REPEATED START condition.
• After the TWI has transmitted SLA+R/W.
• After the TWI has transmitted an address byte.
• After the TWI has lost arbitration.
• After the TWI has been addressed by own slave address or general call.
• After the TWI has received a data byte.
• After a STOP or REPEATED START has been received while still addressed as a Slave.
• When a bus error has occurred due to an illegal START or STOP condition.
STA
5
STO
4
AT89LP51RD2/ED2/ID2 Preliminary
SI
3
Table
Table
Table
19-1.
19-1.
19-1.
AA
2
Reset Value = X000 00XXB
CR1
1
CR0
0
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