PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 85

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

5.2
The large central transmit and receive FIFOs are a major factor according to the system
performance depending on the serial lines and the system bus data rates and latencies.
Programmable thresholds and partitioning of the transmit FIFO alow optimized adaption
to the needs of any application.
5.2.1
The following table provides an overview about all central FIFO related registers. For
detailed register description refer to
Table 16
Offset
Addr.
0044
Data Sheet
H
Access
Type
r/w
Bit-Fields
Pos.
31..27,
26..22,
21..17,
15..11
Central FIFOs Operational Description
Central FIFO Register Overview
Central FIFO Control Registers
Controlled
by
CPU
Name
TFSIZE0
TFSIZE1
TFSIZE2
TFSIZE3
Reset
Value
00000000
Default
0,
0,
0,
0
Chapter
85
H
10.
Register Name
FIFOCR1:
FIFO Control Register 1
Description
Transmit FIFO Section Size i (i=0..3)
Transmit FIFO Section Size for the
corresponding channel i in multiples of 4
DWORDs.
Note: The entire size of all FIFO parts
Note: The minimum FIFO section size
DMA Controller and Central FIFOs
must not exceed 128 DWORDs. If
the complete FIFO is assigned to
only one channel the maximum
size
DWORDs.
for active channels is 4 DWORDs
which means a “1” programmed to
the respective TFSIZEi bit field.
is
limited
to
PEB 20534
PEF 20534
4*31=124
2000-05-30