PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 341

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
(31:0)
Interrupt Mask Bits
Each SCC interrupt event can generate an interrupt vector as well as an
interrupt signal indication to pin INTA. Each bit position of register IMR
is a mask for the corresponding interrupt event in the interrupt status
register ISR. Masked interrupt events neither generate an interrupt
vector nor an interrupt indication to via pin INTA.
bit = ’0’
bit = ’1’
Moreover, masked interrupt events are:
• not displayed in the interrupt status register ISR if bit ’VIS’ in register
• are displayed in interrupt status register ISR if bit ’VIS’ in register
Note: After RESET, all interrupt events are masked.
For detailed interrupt event description refer to the corresponding bit
position in register ISR.
CCR0 is programmed to ’0’.
CCR0 is programmed to ’1’.
The corresponding interrupt event is NOT masked and will
generate an interrupt vector as well as an interrupt
indication via pin INTA.
The corresponding interrupt event is masked and will
NEITHER generate an interrupt vector NOR an interrupt
indication via pin INTA.
341
Detailed Register Description
PEB 20534
PEF 20534
(all modes)
2000-05-30