PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 127

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

6.3
6.3.1
A general purpose 8-/16-bit port is provided on pins GP0...GP15. Every pin is separately
programmable via the General Purpose Port Direction Register GPDIR to operate as an
output or an input.
The number of available port pins depends on the selected MFP configuration mode (bit
field ’PERCFG’ in register GMODE).
If defined as output, the state of the pin is directly controlled via the General Purpose Port
Data Register GPDATA. Read access to this register delivers the current state of all GPP
pins (input and output signals).
If defined as input, the state of the pin is monitored. The value is readable via GPDATA.
All changes may be (if desired) indicated via interrupt. Assigned register: General
Purpose Port Interrupt Mask Register GPIM. See
Page
6.3.2
The GPP block generates interrupts for transitions on each input (and output) signal. Any
pin can be enabled for interrupt generation by setting the corresponding bit of the GPP
Interrupt Mask register GPIM (refer to section
Page
All interrupt events result in an GPP interrupt vector which is transferred into the
peripheral interrupt queue (refer to section
Data Sheet
368.
368) to ‘0‘.
General Purpose Port (GPP) Interface
GPP Functional Description
GPP Interrupt Vector
127
“GPP Interrupt Vector” on Page
“GPP Registers Description” on
“GPP Registers Description” on
Multi Function Port (MFP)
PEB 20534
PEF 20534
2000-05-30
398).