PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 83

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Figure 19
According the interrupt service routine (ISR) two different solutions (or any mix of them)
are possible:
• Traditional ISR entry on interrupt event (INTA signal asserted):
Data Sheet
On interrupt event the CPU jumps to the ISR entry point. Within the ISR the DSCC4
global status register GSTAR is read indicating which interrupt queues store at least
one new interrupt vector. The interrupt indication is confirmed by writing a ’1’ to the
DSCC4 interrupt structure block diagram
HOST Memory interrupt queues
DSCC4 Logical Interrupt Structure
interrupts
receive
SCC0
interrupts
transmit
internal interrupt bus
DWORD
interrupt
central
FIFO
16
(SSC, GPP,
Peripherals
83
LBI)
DMA Controller and Central FIFOs
GSTAR register
Controller
Logic
DMA
INTA
signal
PEB 20534
PEF 20534
2000-05-30