PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 413

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

A data phase may consist of a data transfer and wait cycles. A data phase completes
when data is transferred, which occurs when both IRDY and TRDY are asserted. When
either is deasserted a wait cycle is inserted. In the example below, data is successfully
transferred on clocks 4, 6 and 8, and wait cycles are inserted on clocks 3, 5 and 7. The
first data phase completes in the minimum time for a read transaction. The second data
phase is extended on clock 5 because TRDY is deasserted. The last data phase is
extended because IRDY is deasserted on clock 7.
The Master knows at clock 7 that the next data phase is the last. However, the master is
not ready to complete the last transfer, so IRDY is deasserted on clock 7, and FRAME
stays asserted. Only when IRDY is asserted can FRAME be deasserted, which occurs
on clock 8.
Figure 88
Data Sheet
CLK
FRAME
AD
C/BE
IRDY
TRDY
DEVSEL
1
PCI Read Transaction
Bus CMD
Address
Address
Phase
2
3
Phase
Data
Data 1
4
Bus Transaction
413
5
BE’s
Phase
Data
Data 2
6
Electrical Characteristics
7
Data 3
Phase
Data
8
PEB 20534
PEF 20534
2000-05-30
ITD07575
9