PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 199

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

In normal operation, SYN characters are excluded from storage to receive FIFO. SYN
character length can be specified independently of the selected data character length. If
required, the character parity bit and/or parity status is stored together with each data
byte in the receive FIFO.
As an option, the loading of SYN characters in receive FIFO may be enabled by setting
the bit ’SLOAD’ in register CCR2. Note that in this case SYN characters are treated as
data. Consequently, for correct operation it must be guaranteed that SYN character
length equals the character length + optional parity bit. This is the user’s responsibility
by appropriate software settings.
Filling of the receive FIFO is controlled by a programmable threshold level.
Reception is stopped if
1. the receiver is deactivated by resetting the RAC bit, or
2. the CD signal goes inactive (if Carrier Detect Auto Start is enabled), or
3. the HUNT command is issued again, or
4. the Receiver Reset command (RRES) is issued, or
5. a programmed Termination Character has been found (optional).
On actions 1. and 2., reception remains disabled until the receiver is activated again.
After this is done, and generally in cases 3. and 4., the receiver returns to the (non-
synchronized) Hunt state. In case 5. a HUNT command has to be issued. Reception of
data is internally disabled until synchronization is regained.
Note: Further checking of frame length, extraction of text or data information and
8.3.3
Transmission of data provided in the shared memory is started after the DMA controller
forwards the first data bytes to the SCC transmit FIFO (the LSB is sent out first).
Additionally, the CTS signal may be used to control data transmission. The message
frame is assembled by appending all data characters to the specified SYN character(s)
until Transmit Message End condition is detected (FE indication via DMAC). Internally
generated parity information may be added to each character (SYN, CRC and Preamble
characters are excluded).
If enabled via CRC Append bit (bit ’CAPP’ in register CCR2), the internally calculated
CRC checksum (16 bit) is added to the message frame. Selection between CRC-16 and
CRC-CCITT algorithms is provided.
Note: - Internally generated SYN characters are always excluded from CRC calculation,
The internal CRC generator is automatically initialized before transmission of a new
frame starts. The initialization value is selectable.
Data Sheet
verifying the Frame Checking Sequence (e.g. CRC) has to be done by the
microprocessor.
- CRC checksum (2 bytes) is sent without parity.
Data Transmission
199
Detailed Protocol Description
PEB 20534
PEF 20534
2000-05-30