PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 292

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
CAS
MDS(1..0)
ADM
Carrier Detect Auto Start
CAS = ’0’
CAS = ’1’
Note: (1) In clock modes 1, 4 and 5 this bit must be set to ’0’
Mode Select
This bit field selects the HDLC protocol sub-mode including the
’extended transparent mode’.
MDS = ’00’
MDS = ’01’
MDS = ’10’
MDS = ’11’
Note: MDS(1:0) must be set to ’10’ if PPP operation is selected.
Address Mode Select
The meaning of this bit depends on the selected protocol sub-mode:
Automode, Non-Automode:
Determines the address field length of a HDLC frame.
ADM = ’0’
ADM = ’1’
Address mode 0/1:
Determines whether address mode 0 or 1 is selected.
ADM = ’0’
ADM = ’1’
(2) In ASYNC mode the transmitter is additionally controlled by in-
band flow control mechanism (if enabled).
(3) A receive clock must be provided in order to detect the signal
state of the CD input pin.
The CD pin is used as general input.
In clock mode 1, 4 and 5, clock mode specific control
signals must be provided at this pin (receive strobe,
receive gating RCG, frame sync pulse FSC).
A pull-up/down resistor is recommended if unused.
The CD pin enables/disables the receiver for data
reception. (Polarity of CD pin can be configured via bit
’ICD’.)
Automode.
Non-Automode.
Address Mode 0/1.
(Option ’0’ or ’1’ is selected via bit ’ADM’.)
Extended transparent mode (bit transparent transmission/
reception).
8-bit address field.
16-bit address field.
Address Mode 0 (no address recognition).
Address Mode 1 (high byte address recognition).
292
Detailed Register Description
(hdlc modes)
PEB 20534
PEF 20534
(hdlc mode)
(all modes)
2000-05-30