PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 14

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

List of Tables
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Table 54
Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Data Sheet
PCI Configuration Space: Status/Command Register . . . . . . . . . . . . 224
Status and Command register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . 225
DSCC4 Global Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
GCMDR: Global Command Register . . . . . . . . . . . . . . . . . . . . . . . . . 232
GSTAR: Global Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
GMODE: Global Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
IQLENR0: Interrupt Queue Length Register 0 . . . . . . . . . . . . . . . . . . 246
IQLENR1: Interrupt Queue Length Register 1 . . . . . . . . . . . . . . . . . . 248
IQSCCiRXBAR:
Interrupt Queue SCCi Receiver Base Address Register (i=0...3) . . . 250
IQSCCiTXBAR:
Interrupt Queue SCCi Receiver Base Address Register (i=0...3) . . . 251
IQCFGBAR:
Interrupt Queue Configuration Base Address Register . . . . . . . . . . . 252
IQPBAR:
Interrupt Queue Peripheral Base Address Register. . . . . . . . . . . . . . 253
FIFOCR1: FIFO Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 254
FIFOCR2: FIFO Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 255
FIFOCR3: FIFO Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 257
FIFOCR4: FIFO Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 259
CHiCFG: Channel i Configuration Register (i=3...0) . . . . . . . . . . . . . 261
CHiBRDA:
Channel i Base Receive Descriptor Address Register (i=3...0) . . . . . 264
CHiBTDA:
Channel i Base Transmit Descriptor Address Register (i=3...0) . . . . 265
CHiFRDA:
Channel i First (Current) Receive Descriptor
Address Register (i=3...0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
CHiFTDA:
Channel i First (Current) Transmit Descriptor
Address Register (i=3...0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
CHiLRDA:
Channel i Last Receive Descriptor Address Register (i=3...0). . . . . . 268
CHiLTDA:
Channel i Last Transmit Descriptor Address Register (i=3...0) . . . . . 270
SCC Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
CMDR: Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
STAR: Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
CCR0: Channel Configuration Register 0 . . . . . . . . . . . . . . . . . . . . . 283
CCR1: Channel Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . 288
CCR2: Channel Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . 296
ACCM: PPP ASYNC Control Character Map . . . . . . . . . . . . . . . . . . 306
14
PEB 20534
PEF 20534
2000-05-30
Page