PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 133

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

7.3
Each SCC provides its own transmit and receive FIFOs to handle internal arbitration of
the central FIFOs.
7.3.1
The SCC transmit FIFO is divided into two parts of 6 and 2 DWORDs. The interface
between the two parts provides clock synchronization between the system clock domain
and the protocol logic working with the serial transmit clock.
Figure 39
The 6 DWORDs system clocked FIFO part always requests transmit data from the
central TFIFO if at least 4 DWORDs free space is available even if the SCC is in power-
down condition (register CCR0 bit PU=’0’).
The only exception is a transmit data underrun (XDU) event. In case of an XDU event
(e.g. after excessive PCI bus latency), the FIFO will neither request more data from the
central TFIFO nor transfer another DWORD to the protocol logic.
This XDU blocking mechanism prevents unexpected serial data and must be cleared by
a transmitter reset command. In case of a transmitter reset command (register CMDR
bit XRES=’1’) the complete SCC transmit FIFO is cleared and will immediately request
new transmit data from the central TFIFO.
Transfer of data to the 2 DWORD shadow part only takes place if the SCC is in power-
up condition and an appropriate transmit clock is provided depending on the selected
clock mode.
Serial data transmission will start as soon as at least one DWORD is transferred into the
2 DWORD shadow FIFO and transmission is enabled depending on the selected clock
mode (CTS signal active, clock strobe signal active, valid timeslot or clock gapping signal
inactive).
Data Sheet
data requested
central TFIFO
SCC FIFOs
SCC Transmit FIFO
SCC Transmit FIFO
from
Serial Communication Controller (SCC) Cores
system clock
133
domain
transmit clock
domain
to protocol logic
and serial line
PEB 20534
PEF 20534
2000-05-30