PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 348

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
RFO
FLEX
Receive FIFO Overflow Interrupt
HDLC Mode:
This bit is set to ’1’, if the SCC receive FIFO is full and a complete frame
must be discarded. This interrupt can be used for statistical purposes
and might indicate that the DMAC was not able to service the SCC
receive FIFO quickly enough, e.g. PCI bus latencies are too bad.
ASYNC/BISYNC Mode:
This bit is set to ’1’, if the SCC receive FIFO is full and another received
character must be discarded. This interrupt can be used for statistical
purposes and might indicate that the DMAC was not able to service the
SCC receive FIFO quickly enough, e.g. PCI bus latencies are too bad.
Frame Length Exceeded Interrupt
This bit is set to ’1’, if the frame length check feature is enabled and the
current received frame is aborted because the programmed frame length
limit was exceeded (refer to register RLCR for detailed description).
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Detailed Register Description
PEB 20534
PEF 20534
(hdlc mode)
(all modes)
2000-05-30