PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 354

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
ABM
MCTC(3:0)
LBI Arbitration Master
The DSCC4 (LBI) is always master (initiator) of bus transactions on the
local bus. Nevertheless the local bus can be shared with other master
peripherals. In this case the bus arbitration interface must be enabled by
setting bit ’HDEN’ to ’1’.
Bit ’ABM’ selects whether the DSCC4 (LBI) is arbitration default master
or arbitration slave, i.e. another peripheral is arbitration default bus
master.
ABM=’0’
ABM=’1’
LBI Memory Cycle Time Control
Via this bit field, a constant number of wait states can be selected for
each LBI bus cycle (read and write). The wait states are inserted into the
read and write strobe signal (LRD, LWR) active time (based on LBI clock
cycles):
MCTC
’0000’
’0001’
...
’1111’
Note: The minimum active time of read and write strobe signals is 2 LBI
clocks. MCTC wait states are additional. If LRDY control is
enabled, further wait states may be inserted depending on the
LRDY input signal which is generated by the connected
peripherals.
The DSCC4 (LBI) is arbitration slave. Pin LHDLA of the
bus arbitration interface is an input signal.
The DSCC4 (LBI) is arbitration default master. Pin LHDLA
of the bus arbitration interface is an output signal.
Wait States:
15
14
...
0
354
Detailed Register Description
PEB 20534
PEF 20534
2000-05-30
(-)
(-)