PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 63

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 11
Offset
Addr.
0050
005C
0068
0074
Data Sheet
H
H
H
H
Access
Type
r/w
Bit-Fields
Pos.
27..24
The following commands are evaluated by the DMAC on any action request
(bit ’AR’ set in register GCMDR).
22
21
20
19
DMAC Commands (cont’d)
Controlled
by
CPU
Name
Interrupt
Mask
RDR
IDR
IDT
RDT
Reset
Value
00000000
Default
0
0
0
0
0
63
H
Register Name
CHiCFG (i=0..3):
Channel i Configuration Register
(Page
Description
This bit field is used to mask FI and ERR
interrupt indications distinguished for
transmit and receive DMA channels.
Reset DMA Receiver
Reset DMA Transmitter
Initialize DMA Receiver
Initialize DMA Transmitter
DMA Controller and Central FIFOs
261)
PEB 20534
PEF 20534
2000-05-30