PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 72

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 14
DWORD
1
(read by
DMAC)
2
(read by
DMAC)
3
(read by
DMAC)
Data Sheet
Hold
HI
NO
Next Rx Descr Ptr Next Receive Descriptor Address:
Rx Data Buffer
Ptr
Bit Field
Receive Descriptor Bit Field Description
Description
Hold Indication:
Hold=’1’ marks the end of the descriptor chain. In this
case the DMAC will not branch to the next descriptor
address but stop DMA operation until initialized again
(see
(this bit is ignored if DMAC is configured in last
descriptor address control mode)
Host Initiated Interrupt:
This bit set to ’1’ causes the DMAC to generate an
interrupt after completion of the descriptor and after
transfer of the complete data section to the Host
memory. This may be used for software control
purposes.
Number Of Bytes:
This bit field determines the receive data buffer size and
should be a multiple of 4.
Note: The number of received data bytes includes the
The DMA Channel will branch to this address when
proceeding in the linked list.
Receive Data Buffer Start Address:
The DMA Channel starts writing receive data at this
address. Write access to receive data buffer may occur
per single DWORD transfers or up to 15 DWORDs
burst transfers.
Chapter
receive status byte (RSTA) which is generated by
the SCC receiver in HDLC mode or all status
bytes optionally generated in character oriented
protocol modes respectively.
72
5.1.2.3).
DMA Controller and Central FIFOs
PEB 20534
PEF 20534
2000-05-30