PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 172

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

For receive operation the DSCC4 monitors the incoming data stream for the Opening
Flag (7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of
data and are processed as normal HDLC packet including checking of CRC.
8.1.2.2
The DSCC4 transfers a data block from the shared memory, inserts HDLC Header
(Opening Flag), and appends the HDLC Trailer (CRC, Ending Flag). Beside this
standard HDLC operation, zero-bit stuffing is not performed, but character mapping is
performed.
For receive operation the DSCC4 monitors the incoming data stream for the Opening
Flag (7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of
data and are processed as normal HDLC packet including checking of CRC. Received
mapped characters are unmapped.
8.1.2.3
For transmit operation, the DSCC4 reads a data block from host memory, inserts the
HDLC header (Opening Flag), and appends the HDLC trailer (CRC, Ending Flag). Each
octet (including HDLC framing flags and idle flags) is converted into async character
format (1 start, 8 data bits, 1 stop bit) and then transmitted using the asynchronous
character formatter block.
In receive direction any async character is transferred into the DSCC4’s ASYNC
Character De-Formatting logic block, where it is translated back into the original
information octet. The information octets are then transferred to host the memory as in
HDLC address mode 0 operation.
8.1.3
Characteristics: fully transparent
In extended transparent mode, fully transparent data transmission/reception without
HDLC framing is performed, i.e. without FLAG generation/recognition, CRC generation/
check, or bit stuffing. This allows user specific protocol variations.
In clock mode 1 and clock mode 5 byte alignment is provided.
8.1.4
The following two figures give an overview about the management of the received
frames in the different HDLC operating modes.
Data Sheet
Octet Synchronous PPP
Aynchronous PPP
Extended Transparent Mode
HDLC Receive Data Processing Overview
172
Detailed Protocol Description
PEB 20534
PEF 20534
2000-05-30