PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 347

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
FERR
SCD
PLLA
CDSC
Framing Error Interrupt
This bit is set to ’1’, if a character framing error is detected, i.e. a ’0’ was
ampled at a position where a stop bit ’1’ was expected due to the
selected character format.
SYN Character Detected Interrupt
This bit is set to ’1’, if a synchronization character (SYNC) was detected
after the receiver was switched to HUNT-mode (by command bit ’HUNT’
in register CMDR).
DPLL Asynchronous Interrupt
This bit is only valid, if the receive clock is derived from the internal DPLL
and FM0, FM1 or Manchester data encoding is selected (depending on
the selected clock mode and data encoding mode). It is set to ’1’ if the
DPLL
synchronization has been regained again. If the transmitter is supplied
with a clock derived from the DPLL, transmission is also interrupted.
Carrier Detect Status Change Interrupt
This bit is set to ’1’, if a state transition has been detected at signal CD.
Because only a state transition is indicated via this interrupt, the current
status can be evaluated by reading bit ’CD’ in status register STAR.
has
lost
synchronization.
347
Reception
Detailed Register Description
is
disabled
(bisync mode)
(async mode)
PEB 20534
PEF 20534
(all modes)
(all modes)
2000-05-30
until