PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 12

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

List of Figures
Figure 81
Figure 82
Figure 83
Figure 84
Figure 85
Figure 86
Figure 87
Figure 88
Figure 89
Figure 90
Figure 91
Figure 92
Figure 93
Figure 94
Figure 95
Figure 96
Figure 97
Figure 98
Figure 99
Figure 100
Figure 101
Figure 102
Figure 103
Figure 104
Figure 105
Figure 106
Figure 107
Figure 108
Figure 109
Data Sheet
Interrupt Vector Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . 399
Power-up and Power-down scenarios . . . . . . . . . . . . . . . . . . . . . . . . 406
Power-Failure scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 411
PCI Output Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . 411
PCI Input Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . 412
PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
PCI Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
Master Single READ Transaction followed by a Master Single
WRITE Transaction in De-multiplexed Bus Configuration . . . . . . . . . 418
Master Burst WRITE/READ Access in De-multiplexed
Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Synchronous LBI Read Cycle Timing Multiplexed Bus . . . . . . . . . . . 420
Synchronous LBI Write Cycle Timing Multiplexed Bus . . . . . . . . . . . 420
Synchronous LBI Read Cycle Timing De-multiplexed Bus . . . . . . . . 422
Synchronous LBI Write Cycle Timing De-multiplexed Bus . . . . . . . . 422
LRDY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
LBI Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Clock Input Timing
Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Strobe Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Frame Synchronisation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
High Speed Receive Timing
High Speed Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
SSC Interface Timing (Master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
PEB 20534
PEF 20534
2000-05-30
Page