PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 385

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

HA1…
HA0…
C/R…
LA…
Data Sheet
High Byte Address Compare
Significant only if an HDLC mode with automatic address handling has
been selected. In operating modes which provide high byte address
recognition, the DSCC4 compares the high byte of a 2-byte address with
the contents of two individually programmable addresses (RADR:RAH1,
RADR:RAH2) and the fixed values FE
Dependent on the result of this comparison, the following bit
combinations are possible:
10…RAH1 has been recognized.
00…RAH2 has been recognized.
01…broadcast address has been recognized.
If RAH1, RAH2 contain identical values, a match is indicated by ‘10’.
Command/Response
Significant only if 2-byte address mode has been selected. Value of the
C/R bit (bit in high address byte) in the received frame. The interpretation
depends on the setting of the CRI bit in the RADR register. Refer also to
the description of RADR register.
Low Byte Address Compare
Not significant in transparent and extended transparent operating mode.
the below byte address of a 2-byte address field, or the single address
byte of a 1-byte address field is compared with two addresses
(RADR:RAL1, RADR:RAL2).
0…RAL2 has been recognized.
1…RAL1 has been recognized.
According to the X.25 LAPB protocol, RAL1 is interpreted as the address
of a COMMAND frame and RAL2 is interpreted as the address of a
RESPONSE frame.
385
H
and FC
Host Memory Organization
H
(broadcast address).
PEB 20534
PEF 20534
2000-05-30