PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 327

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 80
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Data Sheet
Bit 31
Bit 15
H
A
B
H
A
B
0
0
0
0
30
14
Receive Mask Address 2 (high)
Receive Mask Address 1 (high)
0
0
0
0
RAMR: Receive Address Mask Register
29
13
0
0
0
0
AMRAH2
AMRAH1
28
12
0
0
0
0
read/write
0000 0000
SCC0
013C
written by CPU, valid in HDLC mode only
evaluated by DSCC4
27
11
0
0
0
0
H
26
10
0
0
0
0
H
SCC1
01BC
25
0
0
9
0
0
24
H
327
0
0
8
0
0
23
7
0
0
0
0
SCC2
023C
22
6
Receive Mask Address 2 (low)
0
0
Receive Mask Address 1 (low)
0
0
H
Detailed Register Description
21
5
0
0
0
0
AMRAL2
AMRAL1
20
4
0
0
0
0
SCC3
02BC
19
3
0
0
0
0
H
18
2
0
0
0
0
PEB 20534
PEF 20534
2000-05-30
17
1
0
0
0
0
16
0
0
0
0
0