Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 93
![Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC32AG20SG
Manufacturer Part Number
Z16FMC32AG20SG
Description
Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC32AG20SG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
0 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC32AG20SG
Manufacturer:
Zilog
Quantity:
160
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- Download datasheet (21Mb)
PS028702-1210
The PWM period is determined by the following equation:
If an initial starting value other than
isters, use the ONE-SHOT mode equation to determine the first PWM timeout period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is determined
by:
If TPOL is set to 1, the ratio of the PWM output High time to the total period is determined
by:
CAPTURE Modes
There are three CAPTURE modes which provide slightly different methods for recording
the time or time interval between timer input events. These modes are CAPTURE mode,
CAPTURE RESTART mode and CAPTURE COMPARE mode. In all the three modes,
when the appropriate timer input transition (capture event) occurs, the timer counter value
is captured and stored in the PWM high and low byte registers. The TPOL bit in the Timer
Control 1 Register determines if the Capture occurs on a rising edge or a falling edge of
the timer input signal. The TICONFIG bit determines whether interrupts are generated on
capture events, reload events, or both. The INCAP bit in Timer Control 0 Register clears
to indicate an interrupt caused by a reload event and sets to indicate the timer interrupt is
caused by an input capture event.
If the timer output alternate function is enabled, the timer output pin changes state (from
Low to High or High to Low) at timer Reload. The initial value is determined by the
TPOL bit.
CAPTURE Mode
When the timer is enabled in CAPTURE mode, it counts continuously and resets to
from
stored in the PWM high and low byte registers, an interrupt is generated and the timer con-
tinues counting. The timer continues counting up to the 16-bit Reload value stored in the
PWM Period(s) =
PWM Output High Time Ration (%) =
PWM Output High Time Ration (%) =
FFFFH
. When the Capture event occurs, the timer counter value is captured and
System Clock Frequency (Hz)
Reload Value x Prescale
P R E L I M I N A R Y
0001H
Reload Value
Reload Value
PWM Value
is loaded into the timer high and low byte reg-
Z16FMC Series Motor Control MCUs
Reload Value
–
x
PWM Value
100
Product Specification
x
100
0000H
Timers
71
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