Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 292

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 152. On-Chip Debugger Commands (Continued)
PS028702-1210
Debug Command
Read Memory (long)
Write Memory (long)
Read Memory CRC
Read Each Memory CRC
Note: Unlisted command byte values are reserved.
Cyclic Redundancy Check
Memory Cyclic Redundancy Check
UART Mode
To ensure transmitted and received data is free of errors, the OCD transmits an 8-bit cyclic
redundancy check (CRC) at the end of each command. The CRC is enabled after the OCD
is initialized, it is not sent with the first read revision command. This CRC is disabled by
clearing the CRCEN bit of the DBGCTL register.
The CRC is reset at the beginning of each command and is computed on the data received
from and sent to the host. The CRC is calculated using the ATM-8 HEC polynomial
x
first. The resulting CRC is reversed and inverted. The check value is
The read memory CRC command computes the CRC on memory in 4K blocks, up to 4K
blocks at a time (16M of data). The Memory CRC is computed using the 16-bit CCITT
polynomial
polynomial LSB first. The resulting CRC is reversed and inverted. The check value is
F0B8h
When the OCD is disabled, the DBG pin is used as a single pin half-duplex UART. When
the serial interface is in UART mode, data received on the single wire bus is written to the
Receive Data Register. Data written to the Transmit Data Register is transmitted on the
single wire bus. In UART mode, the auto-baud hardware is used to configure the BRG, or
the baud rate registers are written to set a specific baud rate.
The UARTEN control bit must be set to 1 to use the serial interface as a UART. Clearing
the UARTEN control bit to zero will prevent data received on the DBG pin from being
written to the Receive Data Register. Clearing the UARTEN control bit to zero also pre-
8
+x
2
+x
.
1
+x
x
0
16
. The CRC is preset to all ones. Data is shifted through the polynomial LSB
+x
12
+x
5
+x
P R E L I M I N A R Y
0
. The CRC is preset to all ones. Data is shifted through the
Command Byte
1010-size[3:0]
1011-size[3:0]
1110-BlockCount[3:0]
1111-BlockCount[3:0]
Z16FMC Series Motor Control MCUs
Disabled by Read Protect
Option Bit
Read only unprotected memory
locations
Write only unprotected memory
locations
–
–
Product Specification
CFh
On-Chip Debugger
.
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