Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 295

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 155. Baud Rate Reload Register (DBGBR)
Table 156. Line Control Register (DBGLCR)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
15:0
Bits
Field
RESET
R/W
ADDR
Bits
7
Baud Rate Reload Register
Line Control Register
Description
RELOAD – This value is the baud rate reload value used to generate a bit clock. It is calcu-
lated as:
Description
OE – Output enable
This bit controls the output driver. If the UART is enabled, this bit controls the output driver dur-
ing transmission only.
0 = Pin is open-drain during UART transmit. Pin behaves as an input if UART is disabled.
1 = Pin is driven during transmission if UART is enabled. Pin is an output if UART is disabled.
15
R/W
OE
7
0
The Baud Rate Reload Register (DBGBR) is used to configure the baud rate of the serial
communication stream. This register is automatically set by the Auto-Baud Detector. This
register cannot be written by the CPU when
The Line Control Register (DBGLCR) controls the state of the UART. This register cannot
be written by the CPU when
RELOAD = SYSTEM CLOCK
14
13
TDH
R/W
6
0
12
BAUD RATE
11
HDS
R/W
5
0
10
P R E L I M I N A R Y
OCDLOCK
FF_E082-FF_E083
9
TXFC
R/W
x 8
4
0
RELOAD
FF_E084
8
0000H
is set.
R/W
OCDLOCK
7
NBEN
R/W
Z16FMC Series Motor Control MCUs
3
0
6
is set.
5
R/W
NB
2
0
4
Product Specification
3
OUT
R/W
On-Chip Debugger
1
1
2
1
PIN
R
X
0
0
273