Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 17

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

List of Tables
PS028702-1210
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Characteristics of the Z16FMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reserved Memory Map Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ZNeo CPU Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reset and Stop Mode Recovery Characteristics and Latency . . . . . . . . . . . 29
System Reset Sources and Resulting Reset Action . . . . . . . . . . . . . . . . . . . 30
Stop Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . . . 34
Reset Status and Control Register (RSTSCR) . . . . . . . . . . . . . . . . . . . . . . . 35
Reset Status Register Values Following Reset . . . . . . . . . . . . . . . . . . . . . . 35
GPIO Port Availability by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Port A–H Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Port A–H Output Data Registers (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 42
Port A–H Data Direction Registers (PxDD) . . . . . . . . . . . . . . . . . . . . . . . . 43
Port A–H High Drive Enable Registers (PxHDE) . . . . . . . . . . . . . . . . . . . . 43
Port A–H Alternate Function High Registers (PxAFH) . . . . . . . . . . . . . . . 44
Port A–H Alternate Function Low Registers (PxAFL) . . . . . . . . . . . . . . . . 44
Alternate Function Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Port A–H Output Control Registers (PxOC) . . . . . . . . . . . . . . . . . . . . . . . . 45
Port A–H Pull-Up Enable Registers (PxPUE) . . . . . . . . . . . . . . . . . . . . . . . 45
Port A–H Stop Mode Recovery Source Enable Registers (PxSMRE) . . . . 46
Port A IRQ MUX1 Register (PAIMUX1) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Port A IRQ MUX Register (PAIMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port A IRQ Edge Register (PAIEDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port C IRQ MUX Register (PCIMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Interrupt Vector placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
System Exception Register High (SYSEXCPH) . . . . . . . . . . . . . . . . . . . . . 53
System Exception Register Low (SYSEXCPL) . . . . . . . . . . . . . . . . . . . . . 54
Last IRQ Register (LASTIRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Interrupt Request 0 Register (IRQ0) and Interrupt Request 0 Set Register
(IRQ0SET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Product Specification
List of Tables
xvii