Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 143

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Note:
Transmitter Interrupts
The transmitter generates a single interrupt when the transmit data register empty bit
(
mission. The TDRE interrupt occurs when the transmitter is initially enabled and after the
transmit shift register has shifted the first bit of a character out. At this point, the transmit
data register is written with the next character to send. This provides 7 bit periods of
latency to load the transmit data register before the transmit shift register completes shift-
ing the current character. Writing to the LIN-UART transmit data register clears the TDRE
bit to 0.
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
In MULTIPROCESSOR mode (
the multiprocessor configuration and the most recent address byte.
•
•
•
•
LIN-UART Overrun Errors
When an overrun error condition occurs, the LIN-UART prevents overwriting of the valid
data currently in the receive data register. The break detect and overrun status bits are not
displayed until the valid data is read.
When the valid data is read, the OE bit of the Status 0 Register is updated to indicate the
overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that
the receive data register contains a data byte. However, because the overrun error
occurred, this byte may not contain valid data and must be ignored. The BRKD bit indi-
cates if the overrun is caused due to a break condition on the line. After reading the status
byte indicating an overrun error, the receive data register must be read again to clear the
error bits in the LIN-UART Status0 register.
TDRE
A data byte is received and is available in the LIN-UART receive data register. This
interrupt is disabled independent of the other receiver interrupt sources using the
RDAIRQ
interrupt occurs after the receive character is placed in the receive data register. To
avoid an overrun error, the software responds to this received data available condition
before the next character is completely received.
A break is received.
A receive data overrun or LIN slave autobaud overrun error is detected.
A data framing error is detected.
A parity error is detected (physical layer error in LIN mode).
) is set to 1. This indicates that the transmitter is ready to accept new data for trans-
bit (this feature is useful in devices, which support DMA). The received data
P R E L I M I N A R Y
MPEN
=
1
), the receive data interrupts are dependent on
Z16FMC Series Motor Control MCUs
Product Specification
LIN-UART
121