Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 52

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

System Reset
PS028702-1210
Note:
During a System Reset, the Z16FMC device is held in Reset for 66 cycles of the IPO. At
the beginning of Reset, all GPIO pins are configured as inputs. All GPIO programmable
pull-ups are disabled.
At the start of a System Reset, the motor control PWM outputs are forced to high-imped-
ance momentarily. When the option bits that control the off-state have been properly eval-
uated, the PWM outputs are forced to the programmed off-state.
During Reset, the Z16FMC CPU and on-chip peripherals are non-active; however, the IPO
and WDT oscillator continue to run. During the first 50 clock cycles, the internal option
bit registers are initialized, after which the system clock for the core and peripherals
begins operating. The Z16FMC CPU and on-chip peripherals remain non-active through
the next 16 cycles of the system clock, after which the internal reset signal is deasserted.
On Reset, control registers within the register file that have a defined reset value are
loaded with their reset values. Other control registers (including the Flags) and general-
purpose RAM are undefined following Reset. The CPU fetches the Reset vector at pro-
gram memory address
cution begins at the Reset vector address.
Table 7 lists the System Reset sources as a function of the operating mode. The following
text provides more detailed information about the individual Reset sources.
A POR/VBO event always maintains priority over all other possible reset sources to
ensure that a full System Reset occurs.
Table 7. System Reset Sources and Resulting Reset Action
Operating Mode
NORMAL or HALT modes
STOP mode
0004H
P R E L I M I N A R Y
and loads that value into the program counter. Program exe-
System Reset Source
POR/VBO
WDT timeout when configured for
Reset
RESET pin assertion
Write RSTSCR[0] to 1
Fault detect logic reset
POR/VBO
RESET pin assertion
Fault detect logic reset
Z16FMC Series Motor Control MCUs
Reset and Stop Mode Recovery
Product Specification
Action
System Reset
System Reset
System Reset
System Reset
System Reset
System Reset
System Reset
System Reset
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