Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 300

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 160. OCD Status Register (OCDSTAT)
PS028702-1210
Bits
6
5
4
3:1
0
Bits
Field
RESET
R/W
Bits
7
OCD Status Register
Description (Continued)
BRKHALT – Breakpoint halt
This bit determines what action the OCD takes when a Breakpoint occurs. If this bit is set to 1,
then the DBGHALT bit is automatically set to 1 when a breakpoint occurs. If BRKHALT is zero,
then the CPU will loop on the breakpoint.
0 = CPU loops on current instruction when breakpoint occurs.
1 = A Breakpoint sets DBGHALT to one.
BRKEN – Enable breakpoints
This bit controls the behavior of the BRK instruction and the hardware breakpoint. By default,
these generate an illegal instruction system trap. If this bit is set to 1, these events generate a
Breakpoint instead of a system trap. The resulting action depends upon the BRKHALT bit.
0 = BRK instruction and hardware breakpoint generates system trap.
1 = BRK instruction and hardware breakpoint generates a breakpoint.
DBGSTOP – Debug Stop mode
This bit controls the system clock behavior in STOP mode. When set to 1, the system clock will
continue to operate in STOP mode.
0 = Stop mode debug disabled. system clock stops in STOP mode.
1 = Stop mode debug enabled. system clock runs in STOP mode.
Reserved
This bit is reserved and must be written to zero.
STEP – Single step an instruction
This bit is used to single step an instruction when in Debug Halt Mode. This bit is automatically
cleared after an instruction is executed.
0 = Idle
1 = Single Step an Instruction.
Description
DBGHALT – Debug Halt mode
This status bit indicates if the CPU is stopped and in debug halt mode.
0 = Device is running
1 = CPU is in Debug Halt mode
DBGHALT DBGBRK
R
7
0
The OCD Status Register (OCDSTAT) reports status information about the current state of
the system.
R
6
0
HALT
R
5
0
P R E L I M I N A R Y
STOP
R
4
0
RPEN
Z16FMC Series Motor Control MCUs
R
3
0
Reserved
R
2
0
Product Specification
TDRF
On-Chip Debugger
R
1
0
RDRE
R
0
1
278