Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 141

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Z16FMC Series Motor Control MCUs
Product Specification
119
software. In the LIN SLAVE mode, the LinState field is updated by hardware as the slave
moves through the Wait for Break, AutoBaud and Active states.
The noise filter is also required to be enabled and configured when interfacing to 
a LIN bus.
LIN MASTER Mode Operation
LIN MASTER mode is selected by setting the bits LMST = 1, LSLV = 0, ABEN = 0, Lin-
State[1:0] = 11b. If the LIN bus protocol indicates the bus is required go into the LIN
Sleep state, the LinState[1:0] bits must be set =
by the software.
00b
The Break is the first part of the message frame transmitted by the master, consisting of at
least 13 bit periods of logical zero on the LIN bus. During initialization of the LIN master,
the duration (in bit times) of the Break is written to the TxBreakLength field of the LIN
control register. The transmission of the Break is performed by setting the
bit in the
SBRK
Control 0 Register. The LIN-UART starts the Break after the
bit is set and any char-
SBRK
acter transmission currently underway has completed. The
bit is deasserted by hard-
SBRK
ware after the break is completed.
The Synch character is transmitted by writing a
to the transmit data register (
55H
TDRE
must be 1 before writing). The Synch character is not transmitted by the hardware until
after the Break is complete.
The Identifier character is transmitted by writing the appropriate value to the transmit data
register (
must be 1 before writing).
TDRE
If the master is sending the response portion of the message, these data and checksum
characters are written to the transmit data register when the TDRE bit asserts.
If the transmit data register is written after TDRE asserts, but before TXE asserts, the
hardware inserts one or two Stop bits between each character as determined by the Stop bit
in the Control 0 Register. Additional idle time occurs between characters if TXE asserts
before the next character is written.
LIN Sleep Mode
While the LIN bus is in the Sleep state, the CPU is in either low power STOP mode, in
HALT mode, or in normal operational state. Any device on the LIN bus issues a Wake-up
message (transmit an
character) if it needs the master to initiate a LIN message frame.
80H
Following the Wake-up message, the master wakes up and initiates a new message.
If the CPU is in STOP mode, the LIN-UART is not active and the Wake-up message must
be detected by a GPIO edge detect Stop Mode Recovery. The duration of the Stop Mode
Recovery sequence may preclude making an accurate measurement of the Wake-up mes-
sage duration.
If the CPU is in HALT or OPERATIONAL mode, the LIN-UART (if enabled) times the
duration of the Wake-up and provides an interrupt following the end of the break sequence
if the duration is  4 bit times. The total duration of the Wake-up message in bit times is
PS028702-1210
P R E L I M I N A R Y
LIN-UART