Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 187

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Table 92. ESPI Mode Register (ESPIMODE)
PS028702-1210
Bits
Field
RESET
R/W
ADDR
Bits
7:5
ESPI Mode Register
Description
SSMD – SLAVE SELECT Mode
This field selects the behavior of SS as a framing signal. For a detailed description of these
modes; see the
000 = SPI mode
When SSIO = 1, the SS pin is driven directly from the SSV bit in the Transmit Data Command
register. The Master software or DMA must set SSV (or a GPIO output if the SS pin is not con-
nected to the appropriate Slave) to the asserted state prior to or on the same clock cycle with
which the transmit data register is written with the initial byte.
At the end of a frame (after the final RDRF event), SSV is deasserted by software. Alterna-
tively, SSV is automatically deasserted by hardware if the TEOF bit in the Transmit Data Com-
mand register is set when the final transmit byte is loaded. In SPI mode, SCK is active only for
data transfer (one clock cycle per bit transferred).
001 = LOOPBACK Mode
When ESPI is configured as Master (MMEN = 1) the outputs are deasserted and data is
looped from shift register out to shift register in. When ESPI is configured as a Slave (MMEN =
0) and SS in asserts, MISO (Slave output) is tied to MOSI (Slave input) to provide an a remote
loop back (echo) function.
010 = I2S Mode
In this mode, the value from SSV will be output by the Master on the SS pin one SCK period
before the data and will remain in that state until the start of the next frame. Typically this mode
is used to send back-to-back frames with SS alternating on each frame. A frame boundary is
indicated in the Master when SSV changes. A frame boundary is detected in the Slave by SS
changing state. The SS framing signal will lead the frame by one SCK period. In this mode
SCK will run continuously, starting with the initial SS assertion. Frames will run back-to-back as
long as software/DMA continue to provide data. The I
carry left and right channel audio data with the SS signal indicating which channel is being
sent. In Slave mode, the change in state of SS (Low to High or High to Low) will trigger the start
of a transaction on the next SCK cycle.
7
The ESPI Mode Register (see Table 92) configures the character bit width and mode of the
ESPI IO pins.
SSMD
R/W
000
Slave Select
6
5
section on page 148.
P R E L I M I N A R Y
4
FF_E263H
NUMBITS[2:0]
R/W
000
Z16FMC Series Motor Control MCUs
3
2
S protocol (Inter IC Sound) is used to
Enhanced Serial Peripheral Interface
2
Product Specification
SSIO
R/W
1
0
SSPO
R/W
0
0
165