Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 279

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Serial Data Format
The data format of the serial interface uses the asynchronous protocol defined in RS-232.
Each character is transmitted as 1 start bit, 8-9 data bits (least-significant bit first) and one
stop bit (see Figure 53).
Each bit time is of same length. The bit period is set by the baud rate generator.
When the transmitter sends a character, it first sends a Low start bit. The transmitter then
waits one bit time. After the start bit is sent, the transmitter sends the next data bit. The
transmitter sends each data bit in turn, waiting one full bit time before sending the next
data bit. After the final data bit is sent, the transmitter sends a high stop bit for one bit
time.
The receiver looks for the falling edge of the start bit. After the receiver sees the start bit is
Low, it waits one half bit time and samples the middle of the start bit. If the middle of the
start bit is High, the receiver considers this as a false start bit. The receiver ignores a false
start bit and searches for another falling edge. If the middle of the start bit is Low, the
receiver considers the start bit valid. The receiver will wait a full bit time from the middle
of the start bit to sample the next data bit. The next data bit is sampled in the middle of the
bit period. The receiver repeats this operation for each data bit, waiting one full bit time to
between sampling each data bit.
Figure 52. Interfacing the serial pin with an RS-232 Interface (2)
ST = Start Bit
SP = Stop Bit
D0-D7 = Data Bits
RS232 TX
RS232 RX
ST
D0
Figure 53. OCD Serial Data Format
D1
RS-232
Tranceiver
P R E L I M I N A R Y
D2
D3
Open-Drain
Buffer
D4
D5
V
Z16FMC Series Motor Control MCUs
DD
10 k
D6

DBG pin
D7
SP
Product Specification
On-Chip Debugger
257