Z16FMC32AG20SG Zilog, Z16FMC32AG20SG Datasheet - Page 180

• Manufacturer Part Number: Z16FMC32AG20SG
• Description: Microcontrollers (MCU) 16BIT 32K FL 2K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC32AG20SG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: 0 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / Rohs Status: Details

Z16FMC Series Motor Control MCUs
Product Specification
158
Error Detection
Error events detected by the ESPI block are described in this section. Error events gener-
ate an ESPI interrupt and set a bit in the ESPI status register. The error bits of the ESPI
Status Register are read/write 1 to clear.
Transmit Underrun
A transmit underrun error occurs for a master with SSMD = 10 or 11 when a character
transfer completes and TDRE = 1. In these modes when a transmit underrun occurs the
transfer is aborted (SCK will halt and SSV will be deasserted). For a master in SPI mode
(
), a transmit underrun is not signaled because SCK will pause and wait for the
SSMD = 00
data register to be written.
In SLAVE mode, a transmit underrun error occurs if TDRE = 1 at the start of a transfer.
When a transmit underrun occurs in SLAVE mode, ESPI transmits a character of all 1s.
A transmit underrun sets the TUND bit in the ESPI status register to 1. Writing 1 to TUND
clears this error flag.
Mode Fault (Multi-Master Collision)
A mode fault indicates when more than one master is trying to communicate at the same
time (a multi-master collision) in SPI mode. The mode fault is detected when the enabled
master’s SS input pin is asserted. For this to happen the control and mode registers must
be configured with MMEN = 1, SSIO = 0 (SS is an input) and SS input = 0. A mode fault
sets the COL bit in the ESPI status register to 1. Writing a 1 to COL clears this error flag.
Receive Overrun
A receive overrun error occurs when a transfer completes and the RDRF bit is still set
from the previous transfer. A receive overrun sets the ROVR bit in the ESPI status register
to 1. Writing 1 to ROVR clears this error flag. The receive data register is not overwritten
and will contain the data from the transfer which initially set the RDRF bit. Subsequent
received data is lost until the RDRF bit is cleared.
Slave Mode Abort
In SLAVE mode of operation if the SS pin deasserts before all bits in a character have
been transferred, the transaction is aborted. When this condition occurs the ABT bit is set
in the ESPI Status Register. A slave abort error resets the slave control logic to the idle
state.
A slave abort error is also asserted in SLAVE mode, if
and a BRG timeout
BRGCTL = 1
occurs. When
is in SLAVE mode, it functions as a WDT monitoring the SCK
BRGCTL = 1
signal. The BRG counter is reloaded every time a transition on SCK occurs while SS is
asserted. The baud rate reload registers must be programmed with a value longer than the
expected time between SS assertion and the first SCK edge, between SCK transitions
PS028702-1210
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface